In conventional semiconductor device manufacturing methods, a design layout obtained by design is subjected to OPC (Optical Proximity Correction) in which corrections are made allowing for distortion due to optical proximity effects in advance; and is converted into a post-OPC layout; and is then written as a mask. Exposure onto a wafer using a mask obtained by writing results in transfer of a design pattern onto the wafer. This transfer of a design pattern does not necessarily use a mask but instead may use a post-OPC layout for direct writing onto a wafer.
The above OPC assumes the occurrence of distortion induced not only during optical lithography but also during other processes such as charged beam lithography, X-ray lithography, etching, CMP, and mask formation.
In general, there is a tradeoff between high-precision OPC processing and the cost of manufacturing a mask or wafer. That is, OPC processing with higher precision tends to increase cost.
Conventionally, rule-based OPC has been used as a main technique for OPC processing. Rule-based OPC uses parameters, such as a unit of correction steps, the number of segments of an object to be corrected, the number of correction stages for corners, the number of correction stages for line ends, and the like, to increase accuracy, but it has a problem that such increase in accuracy increases processing time and manufacturing cost.
Instead of rule-based OPC, model-based OPC has been employed in recent years. As compared to rule-based OPC in which correction rules are described by humans on the basis of pattern features like DRC (Design Rule Checker), model-based OPC uses lithography simulations to make correction while predicting the shapes of patterns formed on a wafer. Although model-based OPC improves accuracy of correction, there is the problem of increasing processing time due to chip-level simulations. The processing time in this case may range from several days to several weeks for the case of using the same processing resources as in conventional cases.
Model-based OPC, as compared to rule-based OPC, generally produces post-OPC layout patterns of more complicated shapes and thus outputs more data. Accordingly, there is the problem of further increasing the processing time required for conversion of post-OPC layouts into mask data and writing onto a wafer.
While model-based OPC uses parameters, such as unit lengths of moving edges along their lengths, the number of those units, the step of movement, and the like, to increase accuracy, such increase in accuracy increases not only resources required for OPC processing but also the number of writing data. Thus, the manufacturing cost tends to increase.
Specifically, either rule-based or model-based OPC has the problem of increasing processing time and manufacturing cost due to increase in accuracy of OPC processing.
To solve the aforementioned problem, several techniques have been suggested for reducing processing time, manufacturing cost, and the like by varying accuracy of OPC processing depending on layout types. Examples of the conventional correction techniques are disclosed for example in the following patent documents 1 to 8.
Patent Document 1: Japanese Patent Application Laid-open No. 10-199785
Patent Document 2: Japanese Patent Application Laid-open No. 10-301255
Patent Document 3: Japanese Patent Application Laid-open No. 2000-162758
Patent Document 4: Japanese Patent Application Laid-open No. 2001-100390
Patent Document 5: Japanese Patent Application Laid-open No. 2002-341514
Patent Document 6: Japanese Patent Application Laid-open No. 2003-173012
Patent Document 7: Japanese Patent Application Laid-open No. 9-319067
Patent Document 8: Japanese Patent Application Laid-open No. 2002-328457
In the conventional OPC techniques, for a memory area of a photomask which corresponds to memory, the accuracy of OPC processing is varied depending on layout types. However, these techniques cannot necessarily be said to be appropriate for a random logic area of a photomask which corresponds to a random logic circuit. Thus, there is the problem that reducing processing time and manufacturing cost may be difficult in semiconductor devices which include random logic circuits.